A communication interface enables data transmission between two or more electronic devices including host and peripheral devices. For example, a mobile industry processor interface (MIPI) is a widely adopted communication interface standard between a host device and a peripheral device, and is prevalent in products such as mobile electronic devices, digital cameras, display devices, and portable tablets and laptop computers. MIPI has standardized interconnect protocol between a host and peripherals and is based on very high-speed serial interface, optimized for power. There are several higher layer standards in MIPI such as a display serial interface (DSI), a camera serial interface (CSI), an interface between radio frequency transceiver integrated circuit and baseband integrated circuit (DigRF), low latency interface (LLI), and so forth along with physical layer specifications such as D-PHY and M-PHY.
D-PHY specification provides a high-speed serial interface solution for communications between various components in an electronic device. The D-PHY solution is capable of expanding a bandwidth of a transmission interface through a low-power consumption approach. For data transmission, the MIPI D-PHY specification defines two modes—a high-speed mode (speed up to 1.5 Gbps) and a low-power mode (speed up to 10 Mbps). The high-speed mode is used for high-speed data (e.g., video data) traffic and low power mode is used for transferring control information. In high-speed mode, there is a source synchronous clock on a separate lane between the host and peripherals. In contrast, the low power mode is achieved through a bidirectional data lane between the host and peripherals and the clock is expected to be extracted from the bidirectional data lane.
Further, in high-speed mode, either non-burst data and continuous clock mode or burst data (transferring data in a fraction of time and then switching to low power mode) and non-continuous clock mode (shutting-off and turning-on clock) may be employed for data transfer. Typically, non-burst data and continuous clock mode is employed with the peripherals having no support for burst data transfer. For peripherals supporting burst data transfer, burst data and non-continuous clock mode is employed as it consumes lower power. The MIPI interface is typically in low-power mode between high-speed data lines or frames during horizontal or vertical blanking time. But, the non-continuous high-speed clock lane shutting-off time parameters with respect to video burst completion on data lanes is defined as static setting (pre-configured time periods) under host control. The host shuts-off (i.e., switches to low-power mode) the high-speed clock lane after completing video burst on data lanes of every line of video frame or end of a video frame, and after waiting for pre-configured time period. Further, the host starts the high-speed clock lane before the next video line of video frame or a new video frame starts. The time period between turning-on high-speed clock lane to starting video burst on data lanes is again based on pre-configured time period, controlled by the host. In other words, at the start of data line or frame, host starts sending clock and after waiting for pre-configured time period starts sending first pixel onwards. Similarly, at the end of data line or frame, host stops sending clock after sending last pixel and after waiting for pre-configured time period.
Typically, this static pre-configured time periods are determined after taking into account worst case scenarios during data transfer. For example, in burst data and non-continuous clock mode, the minimum time period between turning-on clock to high-speed data is about 6 high-speed clock cycles. As per MIPI standard, if a particular protocol at the peripheral side requires more than 6 clock cycles, the master side protocol should ensure that these are transmitted. In one example, the maximum number of cycles needed may be in the range of 1000 or 2000 clock cycles. A given peripheral may have this minimum to maximum variation under various operating conditions. Also, there may be significant variation among various peripherals. As there is variation, the host should set pre-configured time period for worst case maximum scenario, which may be 1000 or 2000 clock cycles in this example. Similarly, the minimum time period between last high-speed data to shutting-off clock is about 52 high-speed clock cycles+60 nano seconds (ns). As per MIPI standard, if a particular peripheral requires more clock cycles than 52 cycles+60 ns to finish reception, the host must supply sufficient clocks to accomplish the reception. In one example, the maximum number of cycles needed may be in the range of 5000 or 6000 clock cycles. A given peripheral may have this minimum to maximum variation under various operating conditions. Also, there may be significant variation among various peripherals. As there is variation, the host should set pre-configured time period for worst case maximum scenario, which may be 5000 or 6000 clock cycles in this example.
However, it is not possible to determine pre-configured timing parameters, which are suitable for a peripheral in various operating conditions and among various peripherals. The host set worst case maximum pre-configured clock cycles (time period) may not be optimal for a given peripheral in various operating conditions or may not be optimal among various peripherals. The given peripheral or different peripherals may require anything between minimum to maximum clock cycles. In cases where peripheral needs lower or substantially lower time periods than host set pre-configured time periods, the clock unnecessarily operates for additional time period, thereby consuming additional power. Hence, in the existing MIPI standard, power dissipation on the high-speed clock lane may not be optimal as shutting-off and turning-on high-speed clock depends on pre-configured time periods, that represents the worst case scenario. Further, the pre-configured values may be suboptimal and pose challenges during design phase as well as when the system is under operation.